# agentee command line reference

```
Electronic design for agents: board spec, symbols and footprints as TOML

Usage: agentee <COMMAND>

Commands:
  check       Load every board, symbol and footprint under PATH and report problems
  drc         Design rule checks of a layout: its rule diagnostics, or every rule with --list
  list        List the items in a project
  show        Print the resolved model of one item as JSON
  render      Render an item to PNG as the viewer draws it
  view        Open the viewer, it reloads when files change
  mcp         Serve the project over MCP on stdio
  new         Write a starter board, symbol, footprint, schematic, layout or sim
  import      Import from the installed KiCad libraries
  search      Search KiCad library names; every word must match Library:Name
  sim         Run a simulation (*.sim.toml): FDTD, dc, thermal, cascade, channel, pdn or logic
  sparam      Analyse a sim result: TDR, mixed mode, crosstalk, passivity and reciprocity
  models      Download the KiCad 3D models (VRML) the project's footprints name, for the 3D view
  fab         Write the fab package for a layout: Gerbers, drill, BOM, placement, notes
  export      Write the board and every part model of a layout as one STEP assembly, for enclosure CAD
  parts       Stock, price and cheaper equivalents for a layout's or schematic's BOM from Mouser and Farnell, with keys in ~/.config/agentee/distributors.toml
  fill        Fill the zones of a layout and store the copper in its file, so loads skip the fill
  route       Route nets of a layout on a grid and append the tracks and vias to its file
  tie         Tie every SMD pad of a plane net (a net with a zone) to its plane with a stub and a via beside the pad, and append them to the layout file
  tune        Meander the short net of every pair over its skew limit and every match group member short of its target, and write the new points into the tracks
  neck        Neck down track ends that enter a pad narrower than the track or break clearance near it: the end becomes a separate narrower track within the class neckdown length
  place       Place the schematic's parts on the board: connectors on edges, holes and fiducials in corners, large chips central, passives clustered by the netlist, then legalised and refined
  silk        Move every failing silk reference to the clear spot check suggests, again until they settle, and hide the ones with nowhere to go when asked
  testpoints  Add a test pad to each net that has no probe access: a TestPoint part in the schematic, a footprint on the probe side near the net's copper, and a routed track (and via) to it
  calc        Trace calculators
  layout      Run the layout engine on a layout: the configured stages in order, then the score per term
  pinswap     Reassign a chip's swappable I/O (same bank, pairs as pairs, clock pins kept on clock pins) to untangle the ratsnest
  stackups    List the fab stackup presets a board's `stackup.preset` can name, or print one
  edit        Edit a schematic, layout or board with commands instead of writing TOML by hand
  docs        Print the file format reference
  help        Print this message or the help of the given subcommand(s)

Options:
  -h, --help     Print help
  -V, --version  Print version
```

## agentee new

```
Write a starter board, symbol, footprint, schematic, layout or sim

Usage: agentee new [OPTIONS] <KIND> <NAME>

Arguments:
  <KIND>  [possible values: board, symbol, footprint, schematic, layout, sim]
  <NAME>  

Options:
  -d, --dir <DIR>        
      --kind <SIM_KIND>  The sim to start from: an FDTD run of a layout, or a logic sim of a schematic [default: fdtd] [possible values: fdtd, logic]
  -h, --help             Print help
```

## agentee check

```
Load every board, symbol and footprint under PATH and report problems

Usage: agentee check [OPTIONS] [PATH]

Arguments:
  [PATH]  [default: .]

Options:
      --item <ITEM>  Only this item
      --info         Also print info notes
      --json         
  -h, --help         Print help
```

## agentee edit

```
Edit a schematic, layout or board with commands instead of writing TOML by hand

Every edit takes the item name and a command. `agentee edit sch help` lists them with their arguments. A list of commands also works: `agentee edit sch -` reads them from stdin, one per line, and `agentee edit sch FILE` from a file, one load, one check at the end. It rewrites the TOML, keeps the comments and layout of the file, and prints the check report of the files it touched.

Pin references are REF.PIN, by number (U1.3) or by a unique pin name (U1.VCC). The pin numbers that came back are in the JSON facts.

Usage: agentee edit [OPTIONS] <TARGET> <NAME> [ARGS]...

Arguments:
  <TARGET>
          schematic, layout or board
          
          [possible values: sch, pcb, board]

  <NAME>
          Item name, `-` for stdin, a script file, or a command

  [ARGS]...
          Arguments of the command

Options:
      --list
          List the item's parts and nets, or its tracks, vias and zones

      --json
          

  -h, --help
          Print help (see a summary with '-h')
```

## agentee list

```
List the items in a project

Usage: agentee list [PATH]

Arguments:
  [PATH]  [default: .]

Options:
  -h, --help  Print help
```

## agentee show

```
Print the resolved model of one item as JSON

Usage: agentee show [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
  -h, --help               Print help
```

## agentee render

```
Render an item to PNG as the viewer draws it

Usage: agentee render [OPTIONS] --out <OUT> <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
  -o, --out <OUT>          
      --width <WIDTH>      [default: 1400]
      --height <HEIGHT>    [default: 900]
      --scale <SCALE>      Pixels per point [default: 1]
      --unit <UNIT>        [default: 1]
      --canvas-only        Only the drawing, no side panels
      --hidden-pins        
      --show <SHOW>        Layers to turn on, comma separated (F.Fab,F.Mask,In1.Cu)
      --hide <HIDE>        Layers to turn off, comma separated
      --region <REGION>    Zoom to x0,y0,x1,y1 in mm
  -h, --help               Print help
```

## agentee view

```
Open the viewer, it reloads when files change

Usage: agentee view [OPTIONS] [PATH]

Arguments:
  [PATH]  [default: .]

Options:
      --select <SELECT>  
      --3d               Open layouts in the 3D view
  -h, --help             Print help
```

## agentee search

```
Search KiCad library names; every word must match Library:Name

Usage: agentee search [OPTIONS] <KIND> [QUERY]...

Arguments:
  <KIND>
          Possible values:
          - symbol
          - footprint
          - board:     A whole .kicad_pcb: board, layout, a netlist schematic, footprints and pin symbols

  [QUERY]...
          

Options:
      --limit <LIMIT>
          [default: 40]

  -h, --help
          Print help (see a summary with '-h')
```

## agentee import

```
Import from the installed KiCad libraries

Usage: agentee import [OPTIONS] <KIND> <SPEC>

Arguments:
  <KIND>
          Possible values:
          - symbol
          - footprint
          - board:     A whole .kicad_pcb: board, layout, a netlist schematic, footprints and pin symbols

  <SPEC>
          Library:Name, a .kicad_sym path with :Name, or a .kicad_mod path

Options:
  -d, --dir <DIR>
          

      --with-footprint
          With a symbol, also import its default footprint

      --footprint <FOOTPRINT>
          With a symbol, import this footprint (Library:Name) and link it

      --footprint-dir <FOOTPRINT_DIR>
          Where footprints go when importing with a symbol
          
          [default: footprints]

      --force
          

  -h, --help
          Print help (see a summary with '-h')
```

## agentee models

```
Download the KiCad 3D models (VRML) the project's footprints name, for the 3D view

Usage: agentee models [PATH]

Arguments:
  [PATH]  [default: .]

Options:
  -h, --help  Print help
```

## agentee stackups

```
List the fab stackup presets a board's `stackup.preset` can name, or print one

Usage: agentee stackups [OPTIONS] [NAME]

Arguments:
  [NAME]  Print this preset's layers as JSON

Options:
      --fab <FAB>              jlcpcb, pcbway or generic
      --layers <LAYERS>        Copper layer count
      --thickness <THICKNESS>  Finished thickness in mm, matched within 10%
      --search <SEARCH>        Substring of the name or description, like 1080 or 2oz
      --json                   
  -h, --help                   Print help
```

## agentee calc

```
Trace calculators

Usage: agentee calc <COMMAND>

Commands:
  trace-width  Minimum track width for a current (IPC-2221)
  serpentine   Meander points that add length to a straight segment
  field        Solve the trace cross-section on the GPU (2D field solver)
  impedance    Impedance on a board layer, or the width for a target
  help         Print this message or the help of the given subcommand(s)

Options:
  -h, --help  Print help
```

## agentee calc trace-width

```
Minimum track width for a current (IPC-2221)

Usage: agentee calc trace-width [OPTIONS] --current <CURRENT>

Options:
      --current <CURRENT>  
      --copper <COPPER>    [default: 1oz]
      --rise <RISE>        [default: 10C]
      --internal           
  -h, --help               Print help
```

## agentee calc impedance

```
Impedance on a board layer, or the width for a target

Usage: agentee calc impedance [OPTIONS]

Options:
  -p, --project <PROJECT>            [default: .]
      --board <BOARD>                
      --layer <LAYER>                
      --width <WIDTH>                
      --gap <GAP>                    
      --coplanar-gap <COPLANAR_GAP>  Gap to the ground pour either side (grounded coplanar, outer layers)
      --target <TARGET>              
      --h <H>                        Dielectric height for a bare microstrip, instead of a board
      --er <ER>                      
      --t <T>                        
  -h, --help                         Print help
```

## agentee calc field

```
Solve the trace cross-section on the GPU (2D field solver)

Usage: agentee calc field [OPTIONS]

Options:
  -p, --project <PROJECT>            [default: .]
      --board <BOARD>                
      --layer <LAYER>                [default: F.Cu]
      --width <WIDTH>                
      --netclass <NETCLASS>          Take width and gaps from this net class
      --gap <GAP>                    
      --coplanar-gap <COPLANAR_GAP>  
      --no-mask                      Leave off the solder mask the stackup puts over outer layers
      --fine                         
      --sweep <SWEEP>                Loss sweep START,STOP,POINTS (log spaced), e.g. 10MHz,20GHz,21
  -h, --help                         Print help
```

## agentee calc serpentine

```
Meander points that add length to a straight segment

Usage: agentee calc serpentine [OPTIONS] --from <FROM> --to <TO> --add <ADD>

Options:
      --from <FROM>            Segment start x,y in mm
      --to <TO>                Segment end x,y in mm
      --add <ADD>              Length to add, e.g. 2.5mm
      --amplitude <AMPLITUDE>  Largest bump height [default: 0.6mm]
      --pitch <PITCH>          Distance between the legs of a bump [default: 0.4mm]
  -h, --help                   Print help
```

## agentee place

```
Place the schematic's parts on the board: connectors on edges, holes and fiducials in corners, large chips central, passives clustered by the netlist, then legalised and refined

Usage: agentee place [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --parts <PARTS>      Parts to place, globs allowed, comma separated; default every part
      --keep-placed        Leave every part that already has a placement where it is
      --side <SIDE>        Sides to place on: F, B or both [default: F]
      --seed <SEED>        Seed for the refinement, the same seed gives the same placement [default: 1]
      --dry-run            Report without writing the file
  -h, --help               Print help
```

## agentee route

```
Route nets of a layout on a grid and append the tracks and vias to its file

Usage: agentee route [OPTIONS] --nets <NETS> <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>      [default: .]
      --nets <NETS>            Nets to route, globs allowed, comma separated or repeated
      --layers <LAYERS>        Copper layers to route on, default every layer
      --grid <GRID>            Grid cell in mm [default: 0.05]
      --via <VIA>              Vias from the board to use, comma separated or repeated, default the net class vias
      --via-cost <VIA_COST>    Cost of a via in mm of track [default: 3]
      --bend-cost <BEND_COST>  Cost of a 45 degree bend in mm of track, three times that for 90 [default: 0.1]
      --pairs                  Route differential pairs as coupled pairs where they fit
      --via-in-pad             Allow vias fully inside SMD pads (filled and capped), default keep them off every pad
      --reroute                Remove the existing tracks and vias of these nets first and route them again
      --dry-run                Report without writing the file
  -h, --help                   Print help
```

## agentee tie

```
Tie every SMD pad of a plane net (a net with a zone) to its plane with a stub and a via beside the pad, and append them to the layout file

Usage: agentee tie [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --nets <NETS>        Plane nets to tie, globs allowed, default every net with a zone
      --dry-run            Report without writing the file
  -h, --help               Print help
```

## agentee tune

```
Meander the short net of every pair over its skew limit and every match group member short of its target, and write the new points into the tracks

Usage: agentee tune [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>      [default: .]
      --nets <NETS>            Nets to tune, globs allowed, comma separated [default: *]
      --amplitude <AMPLITUDE>  Largest bump height in mm, default tries 1.2 mm down to 0.2 mm
      --pitch <PITCH>          Bump pitch in mm, default three track widths
      --dry-run                Report without writing the file
  -h, --help                   Print help
```

## agentee neck

```
Neck down track ends that enter a pad narrower than the track or break clearance near it: the end becomes a separate narrower track within the class neckdown length

Usage: agentee neck [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --nets <NETS>        Nets to neck down, globs allowed, comma separated [default: *]
      --taper              Step the width down in a short chain of segments instead of one neck
      --dry-run            Report without writing the file
  -h, --help               Print help
```

## agentee fill

```
Fill the zones of a layout and store the copper in its file, so loads skip the fill

Usage: agentee fill [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
  -h, --help               Print help
```

## agentee silk

```
Move every failing silk reference to the clear spot check suggests, again until they settle, and hide the ones with nowhere to go when asked

Usage: agentee silk [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --hide               Hide references that have no clear spot
      --dry-run            List the fixes without writing the file
  -h, --help               Print help
```

## agentee testpoints

```
Add a test pad to each net that has no probe access: a TestPoint part in the schematic, a footprint on the probe side near the net's copper, and a routed track (and via) to it

Usage: agentee testpoints [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --nets <NETS>        Nets to give a test pad, globs allowed, comma separated; default the [test] nets
      --side <SIDE>        Probe side, F or B; default the [test] side (B)
      --pitch <PITCH>      Grid the pads sit on and the least spacing between them, mm [default: 2.54]
      --dry-run            List the spots without writing any file
  -h, --help               Print help
```

## agentee pinswap

```
Reassign a chip's swappable I/O (same bank, pairs as pairs, clock pins kept on clock pins) to untangle the ratsnest

Usage: agentee pinswap [OPTIONS] --part <PART> <NAME>

Arguments:
  <NAME>  

Options:
      --part <PART>        
  -p, --project <PROJECT>  [default: .]
      --seed <SEED>        [default: 1]
      --write              Rewrite the schematic pin references
  -h, --help               Print help
```

## agentee layout

```
Run the layout engine on a layout: the configured stages in order, then the score per term

Usage: agentee layout [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --from <FROM>        Start at this stage, keeping the results of the stages before it
      --to <TO>            Stop after this stage
      --only <ONLY>        Run one stage only
      --dry-run            Report without writing the plan into the layout file
      --json               
  -h, --help               Print help
```

## agentee drc

```
Design rule checks of a layout: its rule diagnostics, or every rule with --list

Usage: agentee drc [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --list               Print every rule with its id, category, severity and whether it applies here
      --json               
  -h, --help               Print help
```

## agentee sim

```
Run a simulation (*.sim.toml): FDTD, dc, thermal, cascade, channel, pdn or logic

Usage: agentee sim [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --dry-run            Only mesh it and print the grid, time step and step count
  -h, --help               Print help
```

## agentee sparam

```
Analyse a sim result: TDR, mixed mode, crosstalk, passivity and reciprocity

Usage: agentee sparam [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
      --tdr <TDR>          Port for a TDR (name or number)
      --rise <RISE>        10-90% rise time, default 1.3 / the top frequency
      --pair <PAIR>        Mixed mode: IN+,IN-,OUT+,OUT-
      --xtalk <XTALK>      Crosstalk from one port to another: FROM,TO
  -h, --help               Print help
```

## agentee fab

```
Write the fab package for a layout: Gerbers, drill, BOM, placement, notes

Usage: agentee fab [OPTIONS] --out <OUT> <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
  -o, --out <OUT>          
  -h, --help               Print help
```

## agentee export

```
Write the board and every part model of a layout as one STEP assembly, for enclosure CAD

Usage: agentee export [OPTIONS] --out <OUT> <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>  [default: .]
  -o, --out <OUT>          Output file, .step or .stp
  -h, --help               Print help
```

## agentee parts

```
Stock, price and cheaper equivalents for a layout's or schematic's BOM from Mouser and Farnell, with keys in ~/.config/agentee/distributors.toml

Usage: agentee parts [OPTIONS] <NAME>

Arguments:
  <NAME>  

Options:
  -p, --project <PROJECT>              [default: .]
      --boards <BOARDS>                Boards to buy for [default: 1]
      --distributor <DISTRIBUTOR>      Distributors to ask, comma separated (mouser, farnell), default every one with a key
      --farnell-store <FARNELL_STORE>  Farnell store, e.g. uk.farnell.com, ie.farnell.com, de.farnell.com, www.newark.com
      --refs <REFS>                    Only these references, comma separated
      --no-alternatives                Price what is on the BOM without searching for cheaper equivalents
      --config <CONFIG>                Key file instead of ~/.config/agentee/distributors.toml
      --json                           
  -h, --help                           Print help
```

## agentee mcp

```
Serve the project over MCP on stdio

Usage: agentee mcp [PATH]

Arguments:
  [PATH]  [default: .]

Options:
  -h, --help  Print help
```

## agentee docs

```
Print the file format reference

Usage: agentee docs

Options:
  -h, --help  Print help
```

## agentee edit commands

### agentee edit sch

```
agentee edit sch ITEM COMMAND [args]   (sch = sch:NAME, pcb = pcb:NAME)
agentee edit sch -   commands on stdin, one per line
agentee edit sch FILE   commands from a file; the project needs exactly one schematic for this

  add REF SYMBOL [VALUE] [--footprint FP] [--at X,Y] [--rotation 90] [--mirror] [--unit 2] [--dnp] [--field key=value]
  remove REF ...  or  remove net NAME ...
  move REF X,Y [--rotation 90] [--mirror] [--unit 2]
  set REF [VALUE] [--value V] [--footprint FP] [--unit 2] [--dnp] [--clear dnp,footprint] [--field k=v]
  net NAME [REF.PIN ...] [--class Power] [--style power|label] [--sheet NAME]
  connect REF.PIN ... NET
  disconnect REF.PIN ...
  nc REF.PIN ...
  unnc REF.PIN ...
  note TEXT ...
```

### agentee edit pcb

```
agentee edit pcb ITEM COMMAND [args]   (sch = sch:NAME, pcb = pcb:NAME)
agentee edit pcb -   commands on stdin, one per line
agentee edit pcb FILE   commands from a file; the project needs exactly one layout for this

  place REF [X,Y] [--rotation 90] [--bottom] [--locked]
  unplace REF ...
  track NET LAYER X,Y X,Y ... [--width 0.2mm]
  untrack NET | X,Y X,Y ...
  via NET X,Y [--via std] [--count 1] [--pitch 1.2,0]
  unvia NET X,Y | NET ...
  zone NET [--layers F.Cu,In1.Cu] [--outline X,Y ...] [--priority 1] [--clearance 0.25] [--min-width 0.15mm] [--min-island-area 2.0] [--pad-connection solid|relief|none] [--relief-gap 0.3mm] [--spoke-width 0.3mm] [--relief-tht-only]
  unzone NET ...
  pair NET+ NET- [--max-skew 1mm]
  text STRING [--layer F.SilkS] [--at X,Y] [--size 1.0] [--rotation 90] [--locked]
  fanout REF [--via bga] [--skip-rings 2] [--always GND] [--skip A1] [--nets GND,3V3] [--exclude C2?]
  stitch NET [--via std] [--pitch 2.5mm] [--fence RF_*] [--offset 0.5mm] [--margin 0.6mm] [--outline X,Y ...]
  watermark [--at X,Y] [--layer B.SilkS] [--rotation 90] [--hide]
  test [--nets 3V3,*RST*] [--exclude LED_*] [--side B] [--through-holes] [--no-vias] [--min-test-pad 1.0mm]
  board NAME
  schematic NAME
```

### agentee edit board

```
agentee edit board ITEM COMMAND [args]   (sch = sch:NAME, pcb = pcb:NAME)
agentee edit board -   commands on stdin, one per line
agentee edit board FILE   commands from a file; the project needs exactly one board for this

  class NAME [--track-width 0.2mm] [--clearance 0.2mm] [--via std] [--current 1A] [--max-temp-rise 10C] [--impedance 50ohm] [--impedance-tolerance 10%] [--solver field] [--diff-gap 0.15mm] [--coplanar-gap 0.2mm] [--layers F.Cu] [--max-skew 1mm] [--max-uncoupled 1mm] [--neckdown 1mm] [--width LAYER=WIDTH ...] [--description TEXT]
  unclass NAME ...
  via NAME [--drill 0.3mm] [--diameter 0.6mm] [--type through|blind|buried|microvia] [--from F.Cu] [--to B.Cu] [--fill filled_capped] [--drill-kind laser] [--stacked] [--skip] [--cost 2.0] [--backdrill-from L] [--backdrill-to L] [--backdrill-diameter 0.4mm]
  unvia NAME ...
  outline [--size W,H] [--corner-radius 1mm] [--origin X,Y] [--point X,Y ...]
  cutout [--size W,H] [--origin X,Y] [--point X,Y ...]
  stackup [--preset NAME] [--finish ENIG] [--mask-color green] [--silk-color white] [--roughness 1um] [--layer kind:name:thickness ...]
```