# Logic simulations of a counter and an I2C bus

> Two schematics simulated straight from their netlists: a 74HC161 counting into a 74HC138, and an open-drain I2C bus captured by a 74HC595.

- Parts: 74HC161, 74HC138, 74LVC1G06, 74LVC1G07, 74HC595
- Checks: assertions, setup and hold, contention
- Output: result JSON and VCD

`counter` clocks a 74HC161 into a 74HC138 and checks the decoder outputs at set times and the count on every rising edge.

`i2c` is an open-drain bus: a controller built from two 74LVC1G07, a target that pulls SDA low for its ACK with a 74LVC1G06, 4.7k pull-ups, and a 74HC595 clocked by SCL that captures the byte. The sim checks START, the bits, the ACK, the byte and STOP.

Files: https://github.com/v0l/agentee/tree/master/examples/logic