# agentee file format reference > The key by key reference for every agentee file: board specs, stackups, vias and fab rules, the design rule checks, symbols, footprints, schematics, layouts, simulations and the fab package. ## Basics - [Project files](https://agentee.sh/reference/overview/index.html.md): A project is a directory of TOML files loaded by their suffix: boards, symbols, footprints, schematics, layouts and simulations. - [Editing with agentee edit](https://agentee.sh/reference/edit/index.html.md): The commands that write every key of a schematic, layout or board spec, keep the file’s comments, and check what they changed. - [Units and coordinates](https://agentee.sh/reference/units/index.html.md): Millimetres by default, unit strings for everything else, Y growing down and rotation counter-clockwise on screen. - [Workflow](https://agentee.sh/reference/workflow/index.html.md): The order a design is built in, from importing parts to writing the fab package. ## Board - [Board spec](https://agentee.sh/reference/board/index.html.md): The *.board.toml file: fab preset, outline and cutouts, stackup, via types and net classes with impedance and current targets. - [Stackup presets](https://agentee.sh/reference/stackups/index.html.md): Every JLCPCB impedance build, the PCBWay standard builds and two generic HDI stackups, named by the fab’s own code. - [Lamination](https://agentee.sh/reference/lamination/index.html.md): The build-up sequence of presses and drill steps, derived from the stackup or listed by hand, that decides which vias can be drilled. - [Via types](https://agentee.sh/reference/vias/index.html.md): Through, blind, buried and microvias, stacked and skip vias, controlled depth drilling, backdrills and IPC-4761 via fill. - [Fab rules](https://agentee.sh/reference/rules/index.html.md): Every fab rule key, and the values of the generic, jlcpcb and hdi presets with the line of the fab’s capability page each one comes from. - [Design rule checks](https://agentee.sh/reference/drc/index.html.md): Every layout rule with its id, severity and the condition it runs under: copper, drills, mask, silk, assembly, zones, signals, test access and placement. - [Impedance and loss](https://agentee.sh/reference/impedance/index.html.md): Trace geometry per class and layer, closed form and field solved impedance, differential pairs, and the loss model with roughness and ENIG. ## Parts - [Symbols](https://agentee.sh/reference/symbol/index.html.md): The *.sym.toml file: pins, graphics, generated box bodies, multi-unit symbols and logic levels for the signal check. - [Footprints](https://agentee.sh/reference/footprint/index.html.md): The *.fp.toml file: pad rows, pad shapes and layers, edge pads, zone connections, courtyards, silk and 3D models. - [Graphics](https://agentee.sh/reference/graphics/index.html.md): The shapes symbols, footprints and layouts share: lines, rectangles, polylines, polygons, circles, arcs and text. ## Schematic and layout - [Schematics](https://agentee.sh/reference/schematic/index.html.md): The *.sch.toml file: placed parts, nets as lists of pins, net classes, rails and the signal level check, and sheets for large designs. - [Layouts](https://agentee.sh/reference/layout/index.html.md): The *.pcb.toml file: placements, tracks, vias, fanouts, stitching, zones, cutouts, silk, artwork, test access and the version watermark. - [Automatic placement](https://agentee.sh/reference/placement/index.html.md): agentee place: connectors on edges, large chips central, decoupling caps at their pins, then legalised and refined. - [Autorouting](https://agentee.sh/reference/routing/index.html.md): agentee route, tie, tune and neck: grid routing that keeps class widths, clearances and vias, plane ties, length matching and neck-downs. - [Interfaces](https://agentee.sh/reference/interfaces/index.html.md): What a link must meet, from USB 3 to a 50 ohm RF line: impedance, skew, length, vias, stubs, reference planes and return vias. - [Editing in the viewer](https://agentee.sh/reference/viewer/index.html.md): Moving parts, routing tracks and placing vias by hand in agentee view, saved back into the same TOML. ## Simulation - [FDTD simulation](https://agentee.sh/reference/fdtd/index.html.md): A full-wave FDTD run of a layout on the GPU with lumped ports on pads, giving S-parameters as JSON and Touchstone. - [Channel and eye](https://agentee.sh/reference/channel/index.html.md): A bit stream through an S-parameter path with CTLE, DFE and IBIS drivers and receivers, read as an eye. - [Power distribution network](https://agentee.sh/reference/pdn/index.html.md): The impedance of a power rail from its sinks, decaps and VRM against a target, with the anti-resonances to fix. - [Analysing S-parameters](https://agentee.sh/reference/sparam/index.html.md): TDR, mixed-mode pairs, crosstalk, passivity and reciprocity from any FDTD or cascade result. - [Losses in the FDTD](https://agentee.sh/reference/fdtd-losses/index.html.md): Causal dielectric loss, surface impedance with skin effect, roughness and ENIG nickel, and the edge corrections of the mesh. - [Field maps and emissions](https://agentee.sh/reference/fields/index.html.md): E and H field maps in the first prepreg and the far field, with radiated power and the field at 3 m against FCC class B. - [Cascade](https://agentee.sh/reference/cascade/index.html.md): Vendor S-parameters, noise and linearity dropped into a board sim: gain, noise figure, IIP3, P1dB, SFDR and stability. - [DC drop](https://agentee.sh/reference/dc/index.html.md): Every copper layer solved as a resistive sheet: drop, current density, load voltages and the busiest vias. - [Thermal](https://agentee.sh/reference/thermal/index.html.md): Steady state conduction through FR4, copper and vias with convection from both faces, solved on the GPU. - [Logic simulation](https://agentee.sh/reference/logic/index.html.md): An event-driven sim of a schematic’s digital parts: 74 series models, primitives, stimulus, assertions, setup and hold, VCD out. ## Output - [Importing a KiCad board](https://agentee.sh/reference/kicad-import/index.html.md): agentee import board turns a .kicad_pcb into a board spec, layout, netlist schematic, footprints and symbols. - [Fab package](https://agentee.sh/reference/fab/index.html.md): The Gerbers, drill files, BOM, placement, IPC-D-356 netlist, test points and fab notes agentee fab writes. - [Distributors and pricing](https://agentee.sh/reference/distributors/index.html.md): agentee parts: BOM pricing at Mouser and Farnell and cheaper parts that drop in without a downgrade.