The MCP server

The file format reference for boards, symbols and footprints, with examples. Read this before writing files.

Every board, symbol and footprint in the project with its file and error counts.

The resolved model of one item as JSON: pins with positions, expanded pad arrays, stackup with computed trace geometry, impedance and current analysis.

name

Load the project and report errors and warnings for every item, or one item.

include_info item

Design rule checks of a layout. With list = true: every DRC rule with its id, category, severity, and whether it applies to this board and why. Without: the layout's diagnostics that carry a rule id. Rule ids go in the board's [drc] disable list or severity table.

list name

Render an item to PNG exactly as the viewer shows it and return the image.

canvas_only height hidden_pins hide name region save_to show unit width

Stackup presets for a board's `stackup.preset`: JLCPCB and PCBWay builds and generic HDI builds with layer thicknesses and er. Filter the list, or give name to get one preset's layers.

fab layers name search thickness

Search the installed KiCad libraries by name. Every word must match Library:Name.

kind limit query

Convert a KiCad symbol (Library:Name) into a .sym.toml in the project. with_footprint also imports its default footprint, or give footprint to pick one.

dir footprint force spec with_footprint

Convert a KiCad footprint (Library:Name) into a .fp.toml in the project.

dir force spec

Write a starter file for a board, symbol, footprint, schematic, layout or sim, to edit from. A sim starts as an FDTD run of a layout, or with sim_kind logic as a logic sim of a schematic (clock, reset, a clocked assertion) whose nets you rename.

dir kind name sim_kind

Find the 3D models (STEP or VRML) the project's footprints name, downloading missing KiCad library models into the cache. Reports each model's path and triangle count, or why it is missing.

Trace impedance on a board layer for a width (and pair gap), or the width that hits a target.

board coplanar_gap gap layer target width

Solve a trace cross-section with the GPU field solver: impedance, effective permittivity, C and L per metre, delay. Includes solder mask, thickness, coplanar grounds and differential pairs. Within 0.5% of exact references with fine = true.

board coplanar_gap fine gap layer netclass no_mask sweep width

Minimum track width for a current (IPC-2221).

copper current internal temp_rise

Points for a track that replaces a straight segment and adds a given length as trombone bumps to one side. Paste them into the track's points.

add amplitude from pitch to

Place the layout's parts automatically as a quick start: connectors and edge-mount parts on the board edges (never an RF and a USB connector on one edge unless it must), mounting holes and fiducials in the corners, the largest chips near the centre, each IC's decoupling caps, crystal and pull-ups clustered at the pins they serve, placed by weighted wirelength, then legalised on a 0.05 mm grid with no courtyard overlaps and refined by simulated annealing. Writes at, rotation and side into [[footprints]] and refreshes the stored fills. Parts with locked = true stay put.

dry_run keep_placed name parts seed side

Autoroute the ratsnest of the named nets of a layout on a grid, keeping each class's width, clearance, layers and via, and append the tracks and vias to the layout file. Existing copper is never moved unless reroute is set.

bend_cost dry_run grid layers name nets pairs reroute via via_cost via_in_pad

Tie every SMD pad of a plane net (a net with a [[zones]] entry) to the nearest plane layer with a short stub and a via beside the pad, away from the part body, and append them to the layout file. Use this for ground and supply pads instead of routing tracks between them; `route` with a glob skips plane nets.

dry_run name nets

Length-match a layout: meander the short net of every pair over its skew limit and every match group member short of its target, on the longest segments where the bumps clear every other net, and write the points back into the tracks.

amplitude dry_run name nets pitch

Neck down track ends that enter a pad narrower than the track or break clearance near the pad: the end becomes a separate [[tracks]] entry with an explicit width, the smallest of the class width, the pad's smaller side and the widest that keeps clearance, rounded down to 0.01 mm, never under min_track_width and never longer than the class neckdown. taper steps the width down over a short chain of segments. Stored zone fills are refreshed.

dry_run name nets taper

Fill the zones of a layout and store the copper at the end of its file, so loads and the viewer skip the fill until the zone's copper, clearances or neighbours change.

name

Move every silk reference that check flags to the clear spot it suggests, repeating until the labels settle, and optionally hide the ones that have nowhere to go. Writes label = { at, rotation } or hide = true into the footprints.

dry_run hide name

Add a test pad to each net that needs probe access and has none: a TestPoint part (TestPoint_Pad_D1.0mm footprint, both written into the project if missing) joined to the net in the schematic sheet that lists it, a footprint on the probe side in free space near the net's copper, and an autorouted track and via from the net's copper. Nets default to the layout's [test] nets; impedance and pair nets are skipped.

dry_run name nets pitch side

Run the layout engine on a layout: the configured [engine] phases in order, then the score per term with the worst offenders of each. Phases not implemented yet are listed as skipped.

dry_run from name only to

Run a simulation (*.sim.toml): an FDTD run of a layout on the GPU (ports on pads, lumped models for passives, S-parameters saved as JSON and Touchstone next to the spec), any other kind (dc, thermal, cascade, channel, pdn), or a logic sim of the schematic netlist (stimulus, assertions, setup and hold, a VCD next to the spec). Render the sim afterwards to see the plot or the waveforms.

name

Analyse a finished sim or cascade: passivity and reciprocity, a TDR of one port (impedance against time with a Gaussian edge), mixed-mode Sdd/Scc/Scd for a pair given as IN+,IN-,OUT+,OUT-, and crosstalk FROM,TO in frequency and as a step.

name pair rise tdr xtalk

Write the fab package for a layout into a folder: RS-274X Gerbers (X2) per copper, mask, paste, silk and edge layer, Excellon drills, a zip of those for upload, BOM (generic and JLCPCB), pick-and-place, fab notes and assembly drawings. Refuses while the layout has errors.

name out

Write a layout as one STEP assembly for enclosure CAD: the board as a solid with its drilled holes and cutouts, each part's STEP model embedded and placed, and VRML, generated and missing models as surfaces or boxes. Board bottom at z = 0, X and Y as the layout with Y up.

name out

Price a layout's or schematic's BOM at Mouser and Farnell and find cheaper equivalents: the same part at the other distributor, resistors and ceramic capacitors with the same value, package, tolerance, voltage and dielectric (never a downgrade), generic discretes (2N7002, S1D, SS14, SMAJ..) by name and package, indicator LEDs by colour and package, and the distributor's suggested replacement for parts going obsolete. Costs are at the needed quantity, buying up to a price break when that is cheaper. Keys come from ~/.config/agentee/distributors.toml ([mouser] api_key, [farnell] api_key and store).

alternatives boards distributors farnell_store name refs