FDTD 仿真 - agentee 参考

在 GPU 上对 PCB 布局进行全波 FDTD 运行，在焊盘上设置集总端口，以 JSON 和 Touchstone 格式输出 S 参数。

在 GPU（wgpu）上对 PCB 布局进行全波 FDTD 仿真，给出放置在焊盘上的端口之间的 S 参数。agentee sim NAME 运行仿真，并在规范文件旁边写入 NAME.result.json 和 Touchstone NAME.sNp；查看器和 render 随后显示幅度图和史密斯圆图。

name = "lna-rf"
layout = "lna"
cell = 0.05                    # finest mesh cell in mm, default 0.05; the mesh grades out from copper edges
excite = ["IN", "AMP_OUT"]     # ports to drive, one run each; default all
# region = [0, 0, 30, 20]      # crop to x0, y0, x1, y1 in mm, default the board
# max_steps = 150000
# end_db = 50                  # stop once the field energy is this far under its peak, as openEMS does

[frequency]
start = "100MHz"
stop = "4GHz"
points = 391

[[ports]]
name = "IN"
pad = "J1.1"                   # a lumped port over the whole pad, down to the next copper layer
reference = "In2.Cu"           # or name the layer it returns on, e.g. past a cutout
# impedance = 50

[[models]]                     # C, L and R parts take their schematic value by default
ref = "D3"
capacitor = "0.23pF"           # or inductor = "47nH", resistor = "1k", open = true

铜被建模为每个铜层上的零厚度片（焊盘、走线、作为镀铜柱的过孔、带间距的铺铜填充），介电质取自电路板叠层及其损耗正切，以及 CPML 边界。除端口和集总模型外的部件是开放的。已在 50 欧姆微带线上验证：回波损耗低于 -25 dB，插入损耗低于 0.2 dB，相速度在 Kirschning-Jansen 的 1.2% 以内。