符号 - agentee 参考

*.sym.toml 文件：引脚、图形、生成的框体、多单元符号以及用于信号检查的逻辑电平。

name = "LM358"
reference = "U"                # designator prefix
value = "LM358"                # default: name
description = "Dual op amp"
datasheet = "https://..."
keywords = ["opamp", "dual"]
footprint = "SOIC-8_3.9x4.9mm_P1.27mm"
footprint_filters = ["SOIC*3.9x4.9mm*"]
pin_names = "inside"           # inside | outside | hidden
# pin_name_offset = 0.508
# hide_pin_numbers = true
# power = true                 # a power flag symbol like GND

[[graphics]]
kind = "polygon"
points = [[-5.08, -5.08], [5.08, 0], [-5.08, 5.08]]
fill = "background"            # none | solid | background
unit = 1                       # 0 or absent: drawn in every unit

[[pins]]
number = "3"
name = "+"
type = "input"
at = [-7.62, -2.54]            # the connection point, where wires land
side = "left"                  # left | right | top | bottom of the body
length = 2.54                  # default 2.54
unit = 1
# shape = "inverted"           # line | inverted | clock | inverted_clock | input_low | clock_low | output_low | edge_clock_high | non_logic
# hidden = true

side 指定引脚从元件本体的哪一侧伸出。left 引脚从 at 向右延伸至本体。连接点保持在 1.27 mm 网格上（2.54 mm 更好）。

引脚类型：input、output、bidirectional、tri_state、passive、free、unspecified、power_in、power_out、open_collector、open_emitter、no_connect。

名称使用 ~{...} 表示上划线：~{RESET}。

生成的本体

对于盒状符号，按侧列出引脚，让 agentee 将其放置在网格上并确定本体尺寸。每个条目是一个引脚，或 { gap = N } 以留出 N 个空位。

name = "STM32F103C8"
reference = "U"

[[bodies]]
unit = 1                       # optional, one [[bodies]] per unit
# width = 20.32                # minimum body width
# pin_length = 2.54
left = [
  { number = "7", name = "NRST", type = "input" },
  { gap = 1 },
  { number = "10", name = "PA0", type = "bidirectional" },
]
right = [ { number = "30", name = "PA9", type = "bidirectional" } ]
top = [ { number = "1", name = "VBAT", type = "power_in" } ]
bottom = [ { number = "8", name = "VSS", type = "power_in" } ]

本体和手动放置的 [[pins]] / [[graphics]] 可以混合使用。

多单元符号：为引脚和图形指定 unit。相同的引脚编号只有在具有相同名称（共享引脚）时才能出现在多个单元中。

逻辑电平

符号可以声明其引脚的输入阈值，用于原理图的信号电平检查。[levels] 适用于所有 input 和 bidirectional 引脚；引脚自身的 levels 表按字段覆盖它，并将任何引脚类型纳入检查。

[levels]
supply = "VDD"                 # pin name or number whose rail the % levels scale with
vih = "75%"                    # of the supply; or volts, "2.0V"
vil = "25%"
min = "-0.3V"                  # absolute limits, sums allowed: "100%+0.3V"
max = "100%+0.3V"
leakage = "50nA"               # input leakage, either way
# pull_up = "45k"              # a fixed internal pull to the supply
# pull_down = "45k"

[[pins]]
number = "12"
name = "NRST"
type = "input"
at = [-7.62, 0.0]
side = "left"
levels = { vih = "70%", pull_up = "45k" }

只检查具有电平的引脚；对于没有电平的符号，不做任何假设。

符号

#生成的本体

#逻辑电平

生成的本体

逻辑电平