电源分配网络 - agentee 参考

电源轨的阻抗，相对于目标值，考虑其负载、去耦电容和 VRM，并指出需要修复的反谐振。

电源轨的阻抗，来自 FDTD 仿真在电源轨的电源引脚、去耦焊盘和 VRM 上放置的端口。板级仿真的每个端口都必须被驱动，且必须是负载、去耦电容或 VRM。端口应设置较低的 impedance（0.5 到 1 欧姆），因为电源轨的阻抗远低于 50 欧姆，且从 S11 转换时，50 欧姆参考值会导致精度损失。在仿真自身频带以下，电路板被外推为 L 加上其 S 矩阵在第一个点的直流电阻。

name = "vcc-pdn"
kind = "pdn"
board = "rail"                 # the FDTD sim with the rail's ports
sinks = ["U1_VCC"]             # the load pins, left open like current sources
target = { voltage = "5V", ripple = 1.0, transient = "50mA" }   # or impedance = "20mohm"

[[decaps]]
port = "C3"
ref = "C3"
file = "models/grm155r61a105ke15.s2p"   # a measured one-port, series or shunt fixture
mount = "series"

[[decaps]]
port = "C4"
c = "1uF"
esl = "0.4nH"
esr = "15mohm"

[[vrm]]
port = "VRM"
r = "2mohm"
l = "20nH"

[frequency]                    # the sweep to report over
start = "100kHz"
stop = "1GHz"
points = 200

查看器在对数-对数图上绘制每个负载的 |Z| 与目标值的对比。读数给出峰值阻抗及其与目标值的比较，以及最大的反谐振（即移动去耦电容或改变其值的位置）。在只有一个 VRM 和一个去耦电容的理想节点上，结果与 Z_VRM || Z_decap 在机器精度内一致。